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Searchign results: 74HC10

74HC10 datasheet



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Found: 56      Displaying: 1 - 20
#
Part:
Description:
Manuf.
Package
Pins
T°min
T°max
PDF size
1.
74HC107DDual JK flip-flop with reset; negative-edge trigger
PHLPS
SOT108
-
-
-
53K
2.
74HC107DBDual JK flip-flop with reset; negative-edge trigger
PHLPS
SOT337
-
-
-
53K
3.
74HC107NDual JK flip-flop with reset; negative-edge trigger
PHLPS
SOT27
-
-
-
53K
4.
74HC107PWDual JK flip-flop with reset; negative-edge trigger
PHLPS
SOT402
-
-
-
53K
5.
74HC107PWDual JK flip-flop with reset; negative-edge trigger
PHLPS
SOT402
-
-
-
53K
6.
74HC107UDual JK flip-flop with reset; negative-edge trigger
PHLPS
-
-
-
-
53K
7.
74HC109DDual JK flip-flop with set and reset; positive-edge trigger
PHLPS
SOT109
-
-
-
65K
8.
74HC109DBDual JK flip-flop with set and reset; positive-edge trigger
PHLPS
SOT338
-
-
-
65K
9.
74HC109NDual JK flip-flop with set and reset; positive-edge trigger
PHLPS
SOT38
-
-
-
65K
10.
74HC109UDual JK flip-flop with set and reset; positive-edge trigger
PHLPS
-
-
-
-
65K
11.
74HC109UDual JK flip-flop with set and reset; positive-edge trigger
PHLPS
-
-
-
-
65K
12.
74HC10DBTriple 3-input NAND gate
PHLPS
SOT337
-
-
-
34K
13.
74HC10PWTriple 3-input NAND gate
PHLPS
SOT402
-
-
-
34K
14.
74HC10UTriple 3-input NAND gate
PHLPS
-
-
-
-
34K
15.
CD74HC107E HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET
TI
N
14
-55°C
125°C
56K
16.
CD74HC107M HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET
TI
D
14
-55°C
125°C
56K
17.
CD74HC107M96 HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET
TI
D
14
-55°C
125°C
56K
18.
CD74HC109E HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
TI
N
16
-55°C
125°C
58K
19.
CD74HC109M HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
TI
D
16
-55°C
125°C
58K
20.
CD74HC109M96 HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
TI
D
16
-55°C
125°C
58K
1 2 3


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