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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 61. | 74ACT11008D | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | D | 16 | -40°C | 85°C | 77K |
| 62. | 74ACT11008DR | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | D | 16 | -40°C | 85°C | 77K |
| 63. | 74ACT11008DR | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | D | 16 | -40°C | 85°C | 77K |
| 64. | 74ACT11008N | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | N | 16 | -40°C | 85°C | 77K |
| 65. | 74ACT11008N | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | N | 16 | -40°C | 85°C | 77K |
| 66. | 74ACT11008PWLE | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | PW | 16 | -40°C | 85°C | 77K |
| 67. | 74ACT11008PWLE | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | PW | 16 | -40°C | 85°C | 77K |
| 68. | 74ACT11008PWR | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | PW | 16 | -40°C | 85°C | 77K |
| 69. | 74ACT11008PWR | QUADRUPLE 2-INPUT POSITIVE-AND GATES | TI | PW | 16 | -40°C | 85°C | 77K |
| 70. | 74ACT11074DBR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET | TI | DB | 14 | -40°C | 85°C | 81K |
| 71. | 74ACT11074DR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 14 | -40°C | 85°C | 81K |
| 72. | 74ACT11074N | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET | TI | N | 14 | -40°C | 85°C | 81K |
| 73. | CD54ACT112F3A | DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | J | 16 | -55°C | 125°C | 226K |
| 74. | CD54HCT112F3A | HIGH SPEED CMOS LOGIC DUAL J-K FLIP-FLOPS WITH SET AND RESET, NEGATIVE-EDGE TRIGGER | TI | J | 16 | -55°C | 125°C | 55K |
| 75. | CD74ACT112M | DUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -40°C | 85°C | 226K |
| 76. | CD74ACT112M | DUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -40°C | 85°C | 226K |
| 77. | CD74ACT112M | DUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -40°C | 85°C | 226K |
| 78. | CD74ACT112M96 | DUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -40°C | 85°C | 226K |
| 79. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 80. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
