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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 221. | MC100E451FNR2 | 6-Bit D Reg Diff D and Clk | ON | PLCC | 28 | - | - | 112K |
| 222. | MC100E452FN | 5-Bit D Reg Diff D Clk and Q | ON | PLCC | 28 | - | - | 111K |
| 223. | MC100E452FNR2 | 5-Bit D Reg Diff D Clk and Q | ON | PLCC | 28 | - | - | 111K |
| 224. | MC100LVEL14DW | 1:5 Clock Distribution Chip | ON | SOIC | 20 | - | - | 100K |
| 225. | MC100LVEL14DWR2 | 1:5 Clock Distribution Chip | ON | SOIC | 20 | - | - | 100K |
| 226. | MC100LVEL16D | Differential Receiver | ON | SOIC | 8 | - | - | 58K |
| 227. | MC100LVEL16DR2 | Differential Receiver | ON | SOIC | 8 | - | - | 58K |
| 228. | MC100LVEL17DW | Low-Voltage Quad Differential Line Receiver | ON | SOIC | 20 | - | - | 108K |
| 229. | MC100LVEL17DWR2 | Low-Voltage Quad Differential Line Receiver | ON | SOIC | 20 | - | - | 108K |
| 230. | MC100LVEL37DW | Low Voltage 1:4 Divide by 1/Divide by 2 ECL/PECL Clock Fanout Buffer | ON | SOIC | 20 | - | - | 72K |
| 231. | MC100LVEL37DWR2 | Low Voltage 1:4 Divide by 1/Divide by 2 ECL/PECL Clock Fanout Buffer | ON | SOIC | 20 | - | - | 72K |
| 232. | MC100LVEL38DW | Low Voltage Divide by 2, Divide by 4/6 Clock Generator Chip | ON | SOIC | 20 | - | - | 128K |
| 233. | MC100LVEL38DWR2 | Low Voltage Divide by 2, Divide by 4/6 Clock Generator Chip | ON | SOIC | 20 | - | - | 128K |
| 234. | MC100LVEL39DW | -2/4, -4/6 Clock Generation Chip | ON | SOIC | 20 | - | - | 127K |
| 235. | MC100LVEL39DWR2 | -2/4, -4/6 Clock Generation Chip | ON | SOIC | 20 | - | - | 127K |
| 236. | MC100LVEL40DW | Phase-Frequency Detector | ON | SOIC | 20 | - | - | 72K |
| 237. | MC100LVEL40DWR2 | Phase-Frequency Detector | ON | SOIC | 20 | - | - | 72K |
| 238. | MC100LVEL90DW | Triple ECL to PECL Translator | ON | SOIC | 20 | - | - | 114K |
| 239. | MC100LVEL90DWR2 | Triple ECL to PECL Translator | ON | SOIC | 20 | - | - | 114K |
| 240. | MC100LVEL91DW | Triple PECL to ECL Translator | ON | SOIC | 20 | - | - | 80K |
