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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 501. | CD74AC08E | QUAD 2-INPUT AND GATES | TI | N | 14 | -40°C | 85°C | 30K |
| 502. | CD74AC08M | QUAD 2-INPUT AND GATES | TI | D | 14 | -40°C | 85°C | 30K |
| 503. | CD74HC109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 504. | CD74HC112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 505. | CD74HC112M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 55K |
| 506. | CD74HC73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 507. | CD74HC73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 508. | CD74HC73M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 509. | CD74HCT107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 56K |
| 510. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 511. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 512. | CD74HCT109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 513. | CD74HCT109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 514. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 515. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 516. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 517. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 518. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 519. | CD74HCT73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 520. | CD74HCT73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
