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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 21. | 74HC7403D | 4-Bit x 64-word FIFO register; 3-state | PHLPS | SOT162 | - | - | - | 163K |
| 22. | 74HC7403N | 4-Bit x 64-word FIFO register; 3-state | PHLPS | SOT38 | - | - | - | 163K |
| 23. | 74HC74DB | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT337 | - | - | - | 98K |
| 24. | 74HC74N | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT27 | - | - | - | 98K |
| 25. | 74HC74NB | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT27 | - | - | - | 98K |
| 26. | 74HC74PW | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT402 | - | - | - | 98K |
| 27. | 74HC74U | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | - | - | - | - | 98K |
| 28. | 74LVC74AD | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT108 | - | - | - | 99K |
| 29. | 74LVC74ADB | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT337 | - | - | - | 99K |
| 30. | 74LVC74APW | Dual D-type flip-flop with set and reset; positive-edge trigger | PHLPS | SOT402 | - | - | - | 99K |
| 31. | CD54AC74F3A | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | J | 14 | -55°C | 125°C | 36K |
| 32. | CD54HC74F | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER D FLIP-FLOPS WITH SET AND RESET | TI | J | 14 | -55°C | 125°C | 43K |
| 33. | CD54HC74F | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER D FLIP-FLOPS WITH SET AND RESET | TI | J | 14 | -55°C | 125°C | 43K |
| 34. | CD54HC74F3A | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER D FLIP-FLOPS WITH SET AND RESET | TI | J | 14 | -55°C | 125°C | 43K |
| 35. | CD74AC74E | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | N | 14 | -40°C | 85°C | 36K |
| 36. | CD74AC74M | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | D | 14 | -40°C | 85°C | 36K |
| 37. | CD74AC74M96 | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | D | 14 | -40°C | 85°C | 36K |
| 38. | CD74AC74M96 | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | D | 14 | -40°C | 85°C | 36K |
| 39. | CD74AC74M96 | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | D | 14 | -40°C | 85°C | 36K |
| 40. | CD74HC74E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET | TI | N | 14 | -55°C | 125°C | 43K |
