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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 2061. | CD74HC112M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 55K |
| 2062. | CD74HC73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 2063. | CD74HC73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 2064. | CD74HC73M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 2065. | CD74HCT107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 56K |
| 2066. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 2067. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 2068. | CD74HCT109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 2069. | CD74HCT109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 2070. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 2071. | CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 55K |
| 2072. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 2073. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 2074. | CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 57K |
| 2075. | CD74HCT73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 2076. | CD74HCT73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | D | 14 | -55°C | 125°C | 57K |
| 2077. | SN74HC109DR | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 16 | -40°C | 85°C | 142K |
| 2078. | SN74HC109N | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | N | 16 | -40°C | 85°C | 142K |
| 2079. | SN74HC112D | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 16 | -40°C | 85°C | 94K |
| 2080. | SN74HC112DR | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 16 | -40°C | 85°C | 94K |
