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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 1. | 74HC109D | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT109 | - | - | - | 65K |
| 2. | 74HC109DB | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT338 | - | - | - | 65K |
| 3. | 74HC109N | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT38 | - | - | - | 65K |
| 4. | 74HC109U | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | - | - | - | - | 65K |
| 5. | 74HC109U | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | - | - | - | - | 65K |
| 6. | CD74HC109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 7. | CD74HC109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 8. | CD74HC109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 9. | HD74HC109 | Dual J-K Flip-Flops with Preset and Clear | HIT | DP-16 | - | - | - | 59K |
| 10. | IN74HC109D | Dual J-K flip-flop with set and reset, high-performance silicon-gate CMOS | INTGR | SOIC | 16 | -55°C | 125°C | 104K |
| 11. | IN74HC109N | Dual J-K flip-flop with set and reset, high-performance silicon-gate CMOS | INTGR | Plastic DIP | 16 | -55°C | 125°C | 104K |
| 12. | M74HC109 | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | STM | - | - | - | - | 249K |
| 13. | MC74HC109D | Dual J-K flip-flop with set and reset | MOT | SOIC | 16 | -55°C | 125°C | 186K |
| 14. | MC74HC109D | Dual J-K flip-flop with set and reset | MOT | P-SOIC | 16 | -55°C | 125°C | 186K |
| 15. | MC74HC109N | Dual J-K flip-flop with set and reset | MOT | PDIP | 16 | -55°C | 125°C | 186K |
| 16. | MC74HC109N | Dual J-K flip-flop with set and reset | MOT | P-DIP | 16 | -55°C | 125°C | 186K |
| 17. | SL74HC109D | Dual J-K flip-flop with set and reset. High-performance silicon-gate CMOS. | SLS | SOIC | 16 | -55°C | 125°C | 47K |
| 18. | SL74HC109N | Dual J-K flip-flop with set and reset. High-performance silicon-gate CMOS. | SLS | DIP | 16 | -55°C | 125°C | 47K |
| 19. | SN74HC109DR | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 16 | -40°C | 85°C | 142K |
| 20. | SN74HC109N | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | N | 16 | -40°C | 85°C | 142K |
