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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 21. | MC100LVEL01D | 4-Input OR/NOR Gate | ON | SOIC | 8 | - | - | 71K |
| 22. | MC100LVEL01DR2 | 4-Input OR/NOR Gate | ON | - | - | - | - | 71K |
| 23. | MC100LVEL14DW | 1:5 Clock Distribution Chip | ON | SOIC | 20 | - | - | 100K |
| 24. | MC100LVEL14DWR2 | 1:5 Clock Distribution Chip | ON | SOIC | 20 | - | - | 100K |
| 25. | MC100LVEL16D | Differential Receiver | ON | SOIC | 8 | - | - | 58K |
| 26. | MC100LVEL16DR2 | Differential Receiver | ON | SOIC | 8 | - | - | 58K |
| 27. | MC100LVEL17DW | Low-Voltage Quad Differential Line Receiver | ON | SOIC | 20 | - | - | 108K |
| 28. | MC100LVEL17DWR2 | Low-Voltage Quad Differential Line Receiver | ON | SOIC | 20 | - | - | 108K |
| 29. | MC100LVEL37DW | Low Voltage 1:4 Divide by 1/Divide by 2 ECL/PECL Clock Fanout Buffer | ON | SOIC | 20 | - | - | 72K |
| 30. | MC100LVEL37DWR2 | Low Voltage 1:4 Divide by 1/Divide by 2 ECL/PECL Clock Fanout Buffer | ON | SOIC | 20 | - | - | 72K |
| 31. | MC100LVEL38DW | Low Voltage Divide by 2, Divide by 4/6 Clock Generator Chip | ON | SOIC | 20 | - | - | 128K |
| 32. | MC100LVEL38DWR2 | Low Voltage Divide by 2, Divide by 4/6 Clock Generator Chip | ON | SOIC | 20 | - | - | 128K |
| 33. | MC100LVEL56DW | Dual Differential 2:1 Multiplexer (3.3V) | ON | SOIC | 20 | - | - | 113K |
| 34. | MC100LVEL56DWR2 | Dual Differential 2:1 Multiplexer (3.3V) | ON | SOIC | 20 | - | - | 113K |
| 35. | MC100LVEL58D | 2:1 Multiplexer | ON | SOIC | 8 | - | - | 66K |
| 36. | MC100LVEL58DR2 | 2:1 Multiplexer | ON | SOIC | 8 | - | - | 66K |
| 37. | MC100LVEL59DW | Triple 2:1 Multiplexer (3.3V) | ON | SOIC | 20 | - | - | 98K |
| 38. | MC100LVEL59DWR2 | Triple 2:1 Multiplexer (3.3V) | ON | SOIC | 20 | - | - | 98K |
| 39. | MC100LVELT23D | Dual Differential LVPECL to TTL Translator | ON | SOIC | 8 | - | - | 72K |
| 40. | MC100LVELT23DR2 | Dual Differential LVPECL to TTL Translator | ON | SOIC | 8 | - | - | 72K |
