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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 1. | 74HC109D | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT109 | - | - | - | 65K |
| 2. | 74HC109DB | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT338 | - | - | - | 65K |
| 3. | 74LVC109D | Dual JK(not) flip-flop with set and reset; positive-edge trigger | PHLPS | SOT109 | - | - | - | 103K |
| 4. | 74LVC109DB | Dual JK(not) flip-flop with set and reset; positive-edge trigger | PHLPS | SOT338 | - | - | - | 103K |
| 5. | 74LVC109DB | Dual JK(not) flip-flop with set and reset; positive-edge trigger | PHLPS | SOT338 | - | - | - | 103K |
| 6. | IN74AC109D | Dual J-K flip-flop with set and reset high-speed silicon-gate CMOS | INTGR | SOIC | 16 | -40°C | 85°C | 170K |
| 7. | IN74AC109D | Dual J-K flip-flop with set and reset high-speed silicon-gate CMOS | INTGR | SOIC | 16 | -40°C | 85°C | 170K |
| 8. | IN74HC109D | Dual J-K flip-flop with set and reset, high-performance silicon-gate CMOS | INTGR | SOIC | 16 | -55°C | 125°C | 104K |
| 9. | MC74AC109D | Dual JK positive edge-triggered flip-flop | MOT | P-SOIC | 16 | -40°C | 85°C | 197K |
| 10. | MC74AC109D | Dual JK Positive Edge Triggered Flip Flop | ON | SOIC | 16 | - | - | 197K |
| 11. | MC74AC109DR2 | Dual JK Positive Edge Triggered Flip Flop | ON | SOIC | 16 | - | - | 197K |
| 12. | MC74HC109D | Dual J-K flip-flop with set and reset | MOT | SOIC | 16 | -55°C | 125°C | 186K |
| 13. | MC74HC109D | Dual J-K flip-flop with set and reset | MOT | P-SOIC | 16 | -55°C | 125°C | 186K |
| 14. | SL74HC109D | Dual J-K flip-flop with set and reset. High-performance silicon-gate CMOS. | SLS | SOIC | 16 | -55°C | 125°C | 47K |
| 15. | SN74HC109DR | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | TI | D | 16 | -40°C | 85°C | 142K |
