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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 1. | 74HCT107D | Dual JK flip-flop with reset; negative-edge trigger | PHLPS | SOT108 | - | - | - | 53K |
| 2. | 74HCT107N | Dual JK flip-flop with reset; negative-edge trigger | PHLPS | SOT27 | - | - | - | 53K |
| 3. | 74HCT107U | Dual JK flip-flop with reset; negative-edge trigger | PHLPS | - | - | - | - | 53K |
| 4. | 74HCT107U | Dual JK flip-flop with reset; negative-edge trigger | PHLPS | - | - | - | - | 53K |
| 5. | 74HCT109D | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT109 | - | - | - | 65K |
| 6. | 74HCT109DB | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT338 | - | - | - | 65K |
| 7. | 74HCT109N | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT38 | - | - | - | 65K |
| 8. | 74HCT109PW | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | SOT403 | - | - | - | 65K |
| 9. | 74HCT109U | Dual JK flip-flop with set and reset; positive-edge trigger | PHLPS | - | - | - | - | 65K |
| 10. | 74HCT10D | Triple 3-input NAND gate | PHLPS | SOT108 | - | - | - | 34K |
| 11. | 74HCT10D | Triple 3-input NAND gate | PHLPS | SOT108 | - | - | - | 34K |
| 12. | 74HCT10DB | Triple 3-input NAND gate | PHLPS | SOT337 | - | - | - | 34K |
| 13. | 74HCT10N | Triple 3-input NAND gate | PHLPS | SOT27 | - | - | - | 34K |
| 14. | 74HCT10PW | Triple 3-input NAND gate | PHLPS | SOT402 | - | - | - | 34K |
| 15. | 74HCT10U | Triple 3-input NAND gate | PHLPS | - | - | - | - | 34K |
| 16. | CD74HCT107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | TI | N | 14 | -55°C | 125°C | 56K |
| 17. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 18. | CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | N | 16 | -55°C | 125°C | 58K |
| 19. | CD74HCT109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
| 20. | CD74HCT109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | TI | D | 16 | -55°C | 125°C | 58K |
